Tuesday, 9 February 2016

ubuntu terminal emulator minicom quick commands


sudo minicom - s to setup com port
CTRL + A and then Z for command REf
O to cOnfigure port
Q to exit

remember to reset/restart minicom for changes to take effect

dmesg | grep ttyUSB to search for USB device

Install Digilent Cable drivers on Ubuntu (Zybo|Zedboard)

http://www.xilinx.com/support/answers/59128.html


:/opt/Xilinx/SDSoC/2015.4/Vivado/2015.4/data/xicom/cable_drivers/lin64/install_script/install_drivers$ sudo ./install_digilent.sh


Successfully installed Digilent Cable Drivers

Vivado, SDSoC


cannot access ‘/etc/udev/rules.d/52-xilinx-digilent-usb.rules’: No such file or directory



Friday, 9 October 2015

Xilinx Educational Resources

Xilinx Educational Resources

Xilinx University Program

For universities to get access to software and IP licenses, teaching and training materials, subsidized Xilinx boards, and to request donations.
www.xilinx.com/support/university.html

XUP University workshop material (Presentations, Hands-on labs)
www.xilinx.com/support/university/workshops.html

XUP GitHub

https://github.com/xupgit/

Xilinx forums
forums.xilinx.com

Zynq Resources

www.zynqbook.com Free pdf ebook about the Xilinx Zynq device

www.zedboard.org - some Zedboard resources, but now more targeted at Avnet boards.

www.digilentinc.com purchase Xilinx university boards.

Zynq MOOC videos TU Kaiserslautern
https://ems.eit.uni-kl.de/en/courses/online-courses/xilinx-zynq/
Training:
http://www.googoolia.com/wp/category/zynq-training/

Adam Taylor Blog:
Ebook:
http://www.amazon.com/MicroZed-Chronicles-Zynq-Adam-Taylor-ebook/dp/B00V2GXZQM

Zynq Blogs Useful information and guides to getting started with Zynq.
http://zedboard.org/zynqgeek

http://svenand.blogdrive.com/
http://www.drdobbs.com/embedded-systems/the-kitchen-zynq/240166645
http://billauer.co.il/blog/category/zynq/
https://tingcao.wordpress.com/category/zynq/

Xilinx Open Hardware; European Student Design Contest 

www.openhardware2015.org

Open Hardware Student projects and Videos:
www.openhardware2015.org/2015-finalists.html

Instructables
Hack A day
Dangerous Prototypes
Make.com
ARM Community
Zedboard
Elements 14 Community
Xilinx Forums
Linux community
EDN Design Community
EEV Blog
Electronics-lab community 

Synchronize Multiple FPGA systems
http://www.nutaq.com/blog/multi-channel-synchronization-fpga-based-daq-systems


Wednesday, 30 September 2015

Configure Ethernet adapter with static IP to work with Xilinx SDSoc Zynq board (Zybo)

SDSOC debug of Zynq board with USB Ethernet adapter

To debug with SDSoc, you need to connect a network interface between your host PC and the Zynq development board you are using.
You could plug the board into a network or router and allow the board to obtain an IP via DHCP. 

Alternatively, you can use a USB adapter to connect your host PC directly to the board, and this post describes how you do this.

Procedure
  • Connect the USB adapter and install the driver. 
In windows, configure the network interface to have a static IP (192.168.0.1)

  • Identify the network connection, then go to:
Windows Network connections>  [connection name] and double click to open the status
  • Click on Properties > Internet Protocol Version 4 (TCP/IPv4) > properties
  • Select Use the following IP address
IP address: 162.168.0.1
subnet mask: 255.255.255.0 


  • Boot the Zynq board, and from a command prompt, check the ip

> ifconfig
You should see something similar to this:

eth0      Link encap:Ethernet  HWaddr 00:0A:35:00:01:22
          UP BROADCAST RUNNING MULTICAST  MTU:1500  Metric:1
          RX packets:313 errors:0 dropped:0 overruns:0 frame:0
          TX packets:7 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:23411 (22.8 KiB)  TX bytes:2394 (2.3 KiB)
          Interrupt:143 Base address:0xb000

There is no IP address configured for eth0. (It expects to receive an IP via DHCP)

Set IP address dynamically 

To dynamically change the IP (need to do this every time the board is power cycled)

>ifconfig eth0 192.168.0.10


Set IP address statically

To change the settings for the adapter in the network interfaces settings (saving this to the filesystem will retain the settings after power cycling):
  • Start vi and edit /etc/network/interfaces

>vi /etc/network/interfaces

** Tips for vi; **
se the arrows to navigate to the point in the file you want to edit.
Press i (insert) to move to edit mode, and use delete to remove
Press ESC :wq<enter> to save and quit

  • Modify the file to include:

auto lo
iface lo inet loopback
#
auto eth0
iface eth0 inet static
        address 192.168.0.10
        network 192.168.0.1
        netmask 255.255.255.0

  • Reset the interface

>ip addr flush dev eth0 && ifdown -a && ifup -a

  • Check the IP address:

>ifconfig
eth0      Link encap:Ethernet  HWaddr 00:0A:35:00:01:22
          inet addr:192.168.0.10  Bcast:192.168.0.255  Mask:255.255.255.0
          UP BROADCAST RUNNING MULTICAST  MTU:1500  Metric:1
          RX packets:431 errors:0 dropped:0 overruns:0 frame:0
          TX packets:16 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:30458 (29.7 KiB)  TX bytes:4992 (4.8 KiB)
          Interrupt:143 Base address:0xb000
  
Check connection to host:

>ping 192.168.0.1
PING 192.168.0.1 (192.168.0.1): 56 data bytes
64 bytes from 192.168.0.1: seq=0 ttl=128 time=2.081 ms

J


In SDSoc, create a New Target Connection
Give it a name, and use the IP of the board as the host (192.168.0.10) and click OK. 


You should now be able to debug


Wednesday, 30 January 2013

invalid conversion from ‘void*’ to ‘unsigned char*’


... = malloc(vectorSize*sizeof(unsigned char));

invalid conversion from ‘void*’ to ‘unsigned char*’

Make sure that C is not being compiled as C++ !



Tuesday, 29 January 2013

Make a data entry form in access 2010

To use an Access 2010 form to enter data into a table, (assuming the table already exists)


  • Once the form is created, open the form in Design View.
  • In the properties section, in the Data tab, there is a Data Entry Option, Data Entry
Set Data Entry to Yes and the form will be blank each time it is opened, allowing data to be entered.


Wednesday, 12 September 2012

Zedboard Test Application for GPIO (Including MIO/EMIO)

This post includes C code, and the MHS for a GPIO test example using the Zedboard. Provided here for reference.

------------------------------------------------------------
  C Application
------------------------------------------------------------


/*
 * GPIO Test Application for Zedboard
 *
 * Read from GPIO: U/D/L/R/C Pushbuttons
 *           MIO: PushButtons (BTN8, BTN9) (Pins 50, 51)
 *           EMIO: DipSwitches
 * Write one of these values to the GPIO LEDs
 *
 * MIO and EMIO are on same address
 * MIO pins 0-53 are on banks 1 and 2
 * EMIO are on banks 2 and 3
 * MIO/EMO is initialised with a XGpioPs_Config* pointer and a XGpioPs
 */
#include <stdio.h>
#include "xil_types.h"
#include "xgpio.h"
#include "xparameters.h"
#include "xgpiops.h"

// Define constants for use in GPIO functions
#define CHANNEL_ONE 1

#define BANK_ZERO 0
#define BANK_ONE 1
#define BANK_TWO 2

#define DIRECTION_OUT 1
#define DIRECTION_IN 0

int main()
{
   static XGpio GpioLed; // AXI GPIO
   static XGpio GpioPushbuttons; // AXI GPIO

   static XGpioPs PsIO; // MIO and EMIO
   XGpioPs_Config* PsIO_ConfigPtr;

   // Variables to read GPIO into
   volatile u32 pushbuttons, dipswitches, psPushbuttons;

   int xStatus;

   print("Entering main\n\r");

   //AXI Led GPIO Initialization
   xStatus = XGpio_Initialize(&GpioLed,XPAR_LEDS_DEVICE_ID);
   if(XST_SUCCESS != xStatus){
      print("GPIO LED INIT FAILED\n\r");
      return XST_FAILURE;
   }
   XGpio_SetDataDirection(&GpioLed, CHANNEL_ONE,DIRECTION_OUT);

   //AXI Pushbutton GPIO Initialization
   xStatus = XGpio_Initialize(&GpioPushbuttons,XPAR_PUSHBUTTONS_DEVICE_ID);
   if(XST_SUCCESS != xStatus){
      print("GPIO Pushbuttons INIT FAILED\n\r");
      return XST_FAILURE;
   }
   XGpio_SetDataDirection(&GpioPushbuttons, CHANNEL_ONE,DIRECTION_IN);

   //PS GPIO Intialization
   PsIO_ConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
   if(PsIO_ConfigPtr == NULL){
      print(" PS GPIO INIT FAILED \n\r");
      return XST_FAILURE;
   }

   xStatus = XGpioPs_CfgInitialize(&PsIO,
  PsIO_ConfigPtr,
  PsIO_ConfigPtr->BaseAddr);
   if(XST_SUCCESS != xStatus){
      print(" PS GPIO INIT FAILED \n\r");
   }

   while(1){
  // Read from PushButtons
  pushbuttons = XGpio_DiscreteRead(&GpioPushbuttons, CHANNEL_ONE);
  dipswitches = XGpioPs_Read(&PsIO, BANK_TWO);
  psPushbuttons = (XGpioPs_ReadPin(&PsIO, 51)<<1) | XGpioPs_ReadPin(&PsIO, 50);
  // Write to LEDs
  XGpio_DiscreteWrite(&GpioLed, CHANNEL_ONE, pushbuttons);
   }

  print("Exiting Main\r\n");
  return 0;
}







------------------------------------------------------------
  MHS
------------------------------------------------------------

 PARAMETER VERSION = 2.1.0


 PORT processing_system7_0_MIO = processing_system7_0_MIO, DIR = IO, VEC = [53:0]
 PORT processing_system7_0_PS_SRSTB_pin = processing_system7_0_PS_SRSTB, DIR = I
 PORT processing_system7_0_PS_CLK_pin = processing_system7_0_PS_CLK, DIR = I, SIGIS = CLK
 PORT processing_system7_0_PS_PORB_pin = processing_system7_0_PS_PORB, DIR = I
 PORT processing_system7_0_DDR_Clk = processing_system7_0_DDR_Clk, DIR = IO, SIGIS = CLK
 PORT processing_system7_0_DDR_Clk_n = processing_system7_0_DDR_Clk_n, DIR = IO, SIGIS = CLK
 PORT processing_system7_0_DDR_CKE = processing_system7_0_DDR_CKE, DIR = IO
 PORT processing_system7_0_DDR_CS_n = processing_system7_0_DDR_CS_n, DIR = IO
 PORT processing_system7_0_DDR_RAS_n = processing_system7_0_DDR_RAS_n, DIR = IO
 PORT processing_system7_0_DDR_CAS_n = processing_system7_0_DDR_CAS_n, DIR = IO
 PORT processing_system7_0_DDR_WEB_pin = processing_system7_0_DDR_WEB, DIR = O
 PORT processing_system7_0_DDR_BankAddr = processing_system7_0_DDR_BankAddr, DIR = IO, VEC = [2:0]
 PORT processing_system7_0_DDR_Addr = processing_system7_0_DDR_Addr, DIR = IO, VEC = [14:0]
 PORT processing_system7_0_DDR_ODT = processing_system7_0_DDR_ODT, DIR = IO
 PORT processing_system7_0_DDR_DRSTB = processing_system7_0_DDR_DRSTB, DIR = IO, SIGIS = RST
 PORT processing_system7_0_DDR_DQ = processing_system7_0_DDR_DQ, DIR = IO, VEC = [31:0]
 PORT processing_system7_0_DDR_DM = processing_system7_0_DDR_DM, DIR = IO, VEC = [3:0]
 PORT processing_system7_0_DDR_DQS = processing_system7_0_DDR_DQS, DIR = IO, VEC = [3:0]
 PORT processing_system7_0_DDR_DQS_n = processing_system7_0_DDR_DQS_n, DIR = IO, VEC = [3:0]
 PORT processing_system7_0_DDR_VRN = processing_system7_0_DDR_VRN, DIR = IO
 PORT processing_system7_0_DDR_VRP = processing_system7_0_DDR_VRP, DIR = IO
 PORT clk = processing_system7_0_FCLK_CLK0, DIR = O, SIGIS = CLK, CLK_FREQ = 100000000
 PORT leds_pins = leds_GPIO_IO_O, DIR = O, VEC = [7:0]
 PORT dipswitches_pins = zynq_ps_GPIO, DIR = IO, VEC = [7:0]
 PORT pushbuttons_pins = net_pushbuttons_GPIO_IO_I_pin, DIR = I, VEC = [4:0]


BEGIN processing_system7
 PARAMETER INSTANCE = zynq_ps
 PARAMETER HW_VER = 4.01.a
 PARAMETER C_DDR_RAM_HIGHADDR = 0x1FFFFFFF
 PARAMETER C_EN_EMIO_CAN0 = 0
 PARAMETER C_EN_EMIO_CAN1 = 0
 PARAMETER C_EN_EMIO_ENET0 = 0
 PARAMETER C_EN_EMIO_ENET1 = 0
 PARAMETER C_EN_EMIO_I2C0 = 0
 PARAMETER C_EN_EMIO_I2C1 = 0
 PARAMETER C_EN_EMIO_PJTAG = 0
 PARAMETER C_EN_EMIO_SDIO0 = 0
 PARAMETER C_EN_EMIO_CD_SDIO0 = 0
 PARAMETER C_EN_EMIO_WP_SDIO0 = 0
 PARAMETER C_EN_EMIO_SDIO1 = 0
 PARAMETER C_EN_EMIO_CD_SDIO1 = 0
 PARAMETER C_EN_EMIO_WP_SDIO1 = 0
 PARAMETER C_EN_EMIO_SPI0 = 0
 PARAMETER C_EN_EMIO_SPI1 = 0
 PARAMETER C_EN_EMIO_SRAM_INT = 0
 PARAMETER C_EN_EMIO_TRACE = 0
 PARAMETER C_EN_EMIO_TTC0 = 1
 PARAMETER C_EN_EMIO_TTC1 = 0
 PARAMETER C_EN_EMIO_UART0 = 0
 PARAMETER C_EN_EMIO_UART1 = 0
 PARAMETER C_EN_EMIO_MODEM_UART0 = 0
 PARAMETER C_EN_EMIO_MODEM_UART1 = 0
 PARAMETER C_EN_EMIO_WDT = 0
 PARAMETER C_EN_QSPI = 0
 PARAMETER C_EN_SMC = 0
 PARAMETER C_EN_CAN0 = 0
 PARAMETER C_EN_CAN1 = 0
 PARAMETER C_EN_ENET0 = 0
 PARAMETER C_EN_ENET1 = 0
 PARAMETER C_EN_I2C0 = 0
 PARAMETER C_EN_I2C1 = 0
 PARAMETER C_EN_PJTAG = 0
 PARAMETER C_EN_SDIO0 = 1
 PARAMETER C_EN_SDIO1 = 0
 PARAMETER C_EN_SPI0 = 0
 PARAMETER C_EN_SPI1 = 0
 PARAMETER C_EN_TRACE = 0
 PARAMETER C_EN_TTC0 = 1
 PARAMETER C_EN_TTC1 = 0
 PARAMETER C_EN_UART0 = 0
 PARAMETER C_EN_UART1 = 1
 PARAMETER C_EN_MODEM_UART0 = 0
 PARAMETER C_EN_MODEM_UART1 = 0
 PARAMETER C_EN_USB0 = 0
 PARAMETER C_EN_USB1 = 0
 PARAMETER C_EN_WDT = 0
 PARAMETER C_EN_DDR = 1
 PARAMETER C_EN_GPIO = 1
 PARAMETER C_FCLK_CLK0_FREQ = 100000000
 PARAMETER C_FCLK_CLK1_FREQ = 150000000
 PARAMETER C_FCLK_CLK2_FREQ = 50000000
 PARAMETER C_FCLK_CLK3_FREQ = 50000000
 PARAMETER C_EN_EMIO_GPIO = 1
 PARAMETER C_EMIO_GPIO_WIDTH = 8
 PARAMETER C_USE_CR_FABRIC = 1
 PARAMETER C_USE_M_AXI_GP0 = 1
 BUS_INTERFACE M_AXI_GP0 = axi_interconnect_1
 PORT MIO = processing_system7_0_MIO
 PORT PS_SRSTB = processing_system7_0_PS_SRSTB
 PORT PS_CLK = processing_system7_0_PS_CLK
 PORT PS_PORB = processing_system7_0_PS_PORB
 PORT DDR_Clk = processing_system7_0_DDR_Clk
 PORT DDR_Clk_n = processing_system7_0_DDR_Clk_n
 PORT DDR_CKE = processing_system7_0_DDR_CKE
 PORT DDR_CS_n = processing_system7_0_DDR_CS_n
 PORT DDR_RAS_n = processing_system7_0_DDR_RAS_n
 PORT DDR_CAS_n = processing_system7_0_DDR_CAS_n
 PORT DDR_WEB = processing_system7_0_DDR_WEB
 PORT DDR_BankAddr = processing_system7_0_DDR_BankAddr
 PORT DDR_Addr = processing_system7_0_DDR_Addr
 PORT DDR_ODT = processing_system7_0_DDR_ODT
 PORT DDR_DRSTB = processing_system7_0_DDR_DRSTB
 PORT DDR_DQ = processing_system7_0_DDR_DQ
 PORT DDR_DM = processing_system7_0_DDR_DM
 PORT DDR_DQS = processing_system7_0_DDR_DQS
 PORT DDR_DQS_n = processing_system7_0_DDR_DQS_n
 PORT DDR_VRN = processing_system7_0_DDR_VRN
 PORT DDR_VRP = processing_system7_0_DDR_VRP
 PORT FCLK_CLK0 = processing_system7_0_FCLK_CLK0
 PORT FCLK_RESET0_N = processing_system7_0_FCLK_RESET0_N
 PORT M_AXI_GP0_ACLK = processing_system7_0_FCLK_CLK0
 PORT GPIO_I = net_dipswitches_pins
 PORT GPIO = zynq_ps_GPIO
END

BEGIN axi_gpio
 PARAMETER INSTANCE = leds
 PARAMETER HW_VER = 1.01.b
 PARAMETER C_INTERRUPT_PRESENT = 1
 PARAMETER C_GPIO_WIDTH = 8
 PARAMETER C_BASEADDR = 0x41200000
 PARAMETER C_HIGHADDR = 0x4120ffff
 BUS_INTERFACE S_AXI = axi_interconnect_1
 PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
# PORT GPIO_IO = axi_gpio_0_GPIO_IO
 PORT GPIO_IO_O = leds_GPIO_IO_O
END

# PORT GPIO_IO_O = leds_GPIO_IO_O
BEGIN axi_interconnect
 PARAMETER INSTANCE = axi_interconnect_1
 PARAMETER HW_VER = 1.06.a
 PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
 PORT INTERCONNECT_ACLK = processing_system7_0_FCLK_CLK0
 PORT INTERCONNECT_ARESETN = processing_system7_0_FCLK_RESET0_N
END

BEGIN axi_gpio
 PARAMETER INSTANCE = pushbuttons
 PARAMETER HW_VER = 1.01.b
 PARAMETER C_INTERRUPT_PRESENT = 1
 PARAMETER C_GPIO_WIDTH = 5
 PARAMETER C_BASEADDR = 0x41240000
 PARAMETER C_HIGHADDR = 0x4124ffff
 PARAMETER C_ALL_INPUTS = 1
 BUS_INTERFACE S_AXI = axi_interconnect_1
 PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
# PORT GPIO_IO = axi_gpio_1_GPIO_IO
 PORT GPIO_IO_I = net_pushbuttons_GPIO_IO_I_pin
END

BEGIN axi_timer
 PARAMETER INSTANCE = axi_timer_0
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_BASEADDR = 0x42800000
 PARAMETER C_HIGHADDR = 0x4280ffff
 BUS_INTERFACE S_AXI = axi_interconnect_1
 PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
END




----------------------------------------------------