Wednesday, 12 September 2012

Zedboard Test Application for GPIO (Including MIO/EMIO)

This post includes C code, and the MHS for a GPIO test example using the Zedboard. Provided here for reference.

------------------------------------------------------------
  C Application
------------------------------------------------------------


/*
 * GPIO Test Application for Zedboard
 *
 * Read from GPIO: U/D/L/R/C Pushbuttons
 *           MIO: PushButtons (BTN8, BTN9) (Pins 50, 51)
 *           EMIO: DipSwitches
 * Write one of these values to the GPIO LEDs
 *
 * MIO and EMIO are on same address
 * MIO pins 0-53 are on banks 1 and 2
 * EMIO are on banks 2 and 3
 * MIO/EMO is initialised with a XGpioPs_Config* pointer and a XGpioPs
 */
#include <stdio.h>
#include "xil_types.h"
#include "xgpio.h"
#include "xparameters.h"
#include "xgpiops.h"

// Define constants for use in GPIO functions
#define CHANNEL_ONE 1

#define BANK_ZERO 0
#define BANK_ONE 1
#define BANK_TWO 2

#define DIRECTION_OUT 1
#define DIRECTION_IN 0

int main()
{
   static XGpio GpioLed; // AXI GPIO
   static XGpio GpioPushbuttons; // AXI GPIO

   static XGpioPs PsIO; // MIO and EMIO
   XGpioPs_Config* PsIO_ConfigPtr;

   // Variables to read GPIO into
   volatile u32 pushbuttons, dipswitches, psPushbuttons;

   int xStatus;

   print("Entering main\n\r");

   //AXI Led GPIO Initialization
   xStatus = XGpio_Initialize(&GpioLed,XPAR_LEDS_DEVICE_ID);
   if(XST_SUCCESS != xStatus){
      print("GPIO LED INIT FAILED\n\r");
      return XST_FAILURE;
   }
   XGpio_SetDataDirection(&GpioLed, CHANNEL_ONE,DIRECTION_OUT);

   //AXI Pushbutton GPIO Initialization
   xStatus = XGpio_Initialize(&GpioPushbuttons,XPAR_PUSHBUTTONS_DEVICE_ID);
   if(XST_SUCCESS != xStatus){
      print("GPIO Pushbuttons INIT FAILED\n\r");
      return XST_FAILURE;
   }
   XGpio_SetDataDirection(&GpioPushbuttons, CHANNEL_ONE,DIRECTION_IN);

   //PS GPIO Intialization
   PsIO_ConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
   if(PsIO_ConfigPtr == NULL){
      print(" PS GPIO INIT FAILED \n\r");
      return XST_FAILURE;
   }

   xStatus = XGpioPs_CfgInitialize(&PsIO,
  PsIO_ConfigPtr,
  PsIO_ConfigPtr->BaseAddr);
   if(XST_SUCCESS != xStatus){
      print(" PS GPIO INIT FAILED \n\r");
   }

   while(1){
  // Read from PushButtons
  pushbuttons = XGpio_DiscreteRead(&GpioPushbuttons, CHANNEL_ONE);
  dipswitches = XGpioPs_Read(&PsIO, BANK_TWO);
  psPushbuttons = (XGpioPs_ReadPin(&PsIO, 51)<<1) | XGpioPs_ReadPin(&PsIO, 50);
  // Write to LEDs
  XGpio_DiscreteWrite(&GpioLed, CHANNEL_ONE, pushbuttons);
   }

  print("Exiting Main\r\n");
  return 0;
}







------------------------------------------------------------
  MHS
------------------------------------------------------------

 PARAMETER VERSION = 2.1.0


 PORT processing_system7_0_MIO = processing_system7_0_MIO, DIR = IO, VEC = [53:0]
 PORT processing_system7_0_PS_SRSTB_pin = processing_system7_0_PS_SRSTB, DIR = I
 PORT processing_system7_0_PS_CLK_pin = processing_system7_0_PS_CLK, DIR = I, SIGIS = CLK
 PORT processing_system7_0_PS_PORB_pin = processing_system7_0_PS_PORB, DIR = I
 PORT processing_system7_0_DDR_Clk = processing_system7_0_DDR_Clk, DIR = IO, SIGIS = CLK
 PORT processing_system7_0_DDR_Clk_n = processing_system7_0_DDR_Clk_n, DIR = IO, SIGIS = CLK
 PORT processing_system7_0_DDR_CKE = processing_system7_0_DDR_CKE, DIR = IO
 PORT processing_system7_0_DDR_CS_n = processing_system7_0_DDR_CS_n, DIR = IO
 PORT processing_system7_0_DDR_RAS_n = processing_system7_0_DDR_RAS_n, DIR = IO
 PORT processing_system7_0_DDR_CAS_n = processing_system7_0_DDR_CAS_n, DIR = IO
 PORT processing_system7_0_DDR_WEB_pin = processing_system7_0_DDR_WEB, DIR = O
 PORT processing_system7_0_DDR_BankAddr = processing_system7_0_DDR_BankAddr, DIR = IO, VEC = [2:0]
 PORT processing_system7_0_DDR_Addr = processing_system7_0_DDR_Addr, DIR = IO, VEC = [14:0]
 PORT processing_system7_0_DDR_ODT = processing_system7_0_DDR_ODT, DIR = IO
 PORT processing_system7_0_DDR_DRSTB = processing_system7_0_DDR_DRSTB, DIR = IO, SIGIS = RST
 PORT processing_system7_0_DDR_DQ = processing_system7_0_DDR_DQ, DIR = IO, VEC = [31:0]
 PORT processing_system7_0_DDR_DM = processing_system7_0_DDR_DM, DIR = IO, VEC = [3:0]
 PORT processing_system7_0_DDR_DQS = processing_system7_0_DDR_DQS, DIR = IO, VEC = [3:0]
 PORT processing_system7_0_DDR_DQS_n = processing_system7_0_DDR_DQS_n, DIR = IO, VEC = [3:0]
 PORT processing_system7_0_DDR_VRN = processing_system7_0_DDR_VRN, DIR = IO
 PORT processing_system7_0_DDR_VRP = processing_system7_0_DDR_VRP, DIR = IO
 PORT clk = processing_system7_0_FCLK_CLK0, DIR = O, SIGIS = CLK, CLK_FREQ = 100000000
 PORT leds_pins = leds_GPIO_IO_O, DIR = O, VEC = [7:0]
 PORT dipswitches_pins = zynq_ps_GPIO, DIR = IO, VEC = [7:0]
 PORT pushbuttons_pins = net_pushbuttons_GPIO_IO_I_pin, DIR = I, VEC = [4:0]


BEGIN processing_system7
 PARAMETER INSTANCE = zynq_ps
 PARAMETER HW_VER = 4.01.a
 PARAMETER C_DDR_RAM_HIGHADDR = 0x1FFFFFFF
 PARAMETER C_EN_EMIO_CAN0 = 0
 PARAMETER C_EN_EMIO_CAN1 = 0
 PARAMETER C_EN_EMIO_ENET0 = 0
 PARAMETER C_EN_EMIO_ENET1 = 0
 PARAMETER C_EN_EMIO_I2C0 = 0
 PARAMETER C_EN_EMIO_I2C1 = 0
 PARAMETER C_EN_EMIO_PJTAG = 0
 PARAMETER C_EN_EMIO_SDIO0 = 0
 PARAMETER C_EN_EMIO_CD_SDIO0 = 0
 PARAMETER C_EN_EMIO_WP_SDIO0 = 0
 PARAMETER C_EN_EMIO_SDIO1 = 0
 PARAMETER C_EN_EMIO_CD_SDIO1 = 0
 PARAMETER C_EN_EMIO_WP_SDIO1 = 0
 PARAMETER C_EN_EMIO_SPI0 = 0
 PARAMETER C_EN_EMIO_SPI1 = 0
 PARAMETER C_EN_EMIO_SRAM_INT = 0
 PARAMETER C_EN_EMIO_TRACE = 0
 PARAMETER C_EN_EMIO_TTC0 = 1
 PARAMETER C_EN_EMIO_TTC1 = 0
 PARAMETER C_EN_EMIO_UART0 = 0
 PARAMETER C_EN_EMIO_UART1 = 0
 PARAMETER C_EN_EMIO_MODEM_UART0 = 0
 PARAMETER C_EN_EMIO_MODEM_UART1 = 0
 PARAMETER C_EN_EMIO_WDT = 0
 PARAMETER C_EN_QSPI = 0
 PARAMETER C_EN_SMC = 0
 PARAMETER C_EN_CAN0 = 0
 PARAMETER C_EN_CAN1 = 0
 PARAMETER C_EN_ENET0 = 0
 PARAMETER C_EN_ENET1 = 0
 PARAMETER C_EN_I2C0 = 0
 PARAMETER C_EN_I2C1 = 0
 PARAMETER C_EN_PJTAG = 0
 PARAMETER C_EN_SDIO0 = 1
 PARAMETER C_EN_SDIO1 = 0
 PARAMETER C_EN_SPI0 = 0
 PARAMETER C_EN_SPI1 = 0
 PARAMETER C_EN_TRACE = 0
 PARAMETER C_EN_TTC0 = 1
 PARAMETER C_EN_TTC1 = 0
 PARAMETER C_EN_UART0 = 0
 PARAMETER C_EN_UART1 = 1
 PARAMETER C_EN_MODEM_UART0 = 0
 PARAMETER C_EN_MODEM_UART1 = 0
 PARAMETER C_EN_USB0 = 0
 PARAMETER C_EN_USB1 = 0
 PARAMETER C_EN_WDT = 0
 PARAMETER C_EN_DDR = 1
 PARAMETER C_EN_GPIO = 1
 PARAMETER C_FCLK_CLK0_FREQ = 100000000
 PARAMETER C_FCLK_CLK1_FREQ = 150000000
 PARAMETER C_FCLK_CLK2_FREQ = 50000000
 PARAMETER C_FCLK_CLK3_FREQ = 50000000
 PARAMETER C_EN_EMIO_GPIO = 1
 PARAMETER C_EMIO_GPIO_WIDTH = 8
 PARAMETER C_USE_CR_FABRIC = 1
 PARAMETER C_USE_M_AXI_GP0 = 1
 BUS_INTERFACE M_AXI_GP0 = axi_interconnect_1
 PORT MIO = processing_system7_0_MIO
 PORT PS_SRSTB = processing_system7_0_PS_SRSTB
 PORT PS_CLK = processing_system7_0_PS_CLK
 PORT PS_PORB = processing_system7_0_PS_PORB
 PORT DDR_Clk = processing_system7_0_DDR_Clk
 PORT DDR_Clk_n = processing_system7_0_DDR_Clk_n
 PORT DDR_CKE = processing_system7_0_DDR_CKE
 PORT DDR_CS_n = processing_system7_0_DDR_CS_n
 PORT DDR_RAS_n = processing_system7_0_DDR_RAS_n
 PORT DDR_CAS_n = processing_system7_0_DDR_CAS_n
 PORT DDR_WEB = processing_system7_0_DDR_WEB
 PORT DDR_BankAddr = processing_system7_0_DDR_BankAddr
 PORT DDR_Addr = processing_system7_0_DDR_Addr
 PORT DDR_ODT = processing_system7_0_DDR_ODT
 PORT DDR_DRSTB = processing_system7_0_DDR_DRSTB
 PORT DDR_DQ = processing_system7_0_DDR_DQ
 PORT DDR_DM = processing_system7_0_DDR_DM
 PORT DDR_DQS = processing_system7_0_DDR_DQS
 PORT DDR_DQS_n = processing_system7_0_DDR_DQS_n
 PORT DDR_VRN = processing_system7_0_DDR_VRN
 PORT DDR_VRP = processing_system7_0_DDR_VRP
 PORT FCLK_CLK0 = processing_system7_0_FCLK_CLK0
 PORT FCLK_RESET0_N = processing_system7_0_FCLK_RESET0_N
 PORT M_AXI_GP0_ACLK = processing_system7_0_FCLK_CLK0
 PORT GPIO_I = net_dipswitches_pins
 PORT GPIO = zynq_ps_GPIO
END

BEGIN axi_gpio
 PARAMETER INSTANCE = leds
 PARAMETER HW_VER = 1.01.b
 PARAMETER C_INTERRUPT_PRESENT = 1
 PARAMETER C_GPIO_WIDTH = 8
 PARAMETER C_BASEADDR = 0x41200000
 PARAMETER C_HIGHADDR = 0x4120ffff
 BUS_INTERFACE S_AXI = axi_interconnect_1
 PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
# PORT GPIO_IO = axi_gpio_0_GPIO_IO
 PORT GPIO_IO_O = leds_GPIO_IO_O
END

# PORT GPIO_IO_O = leds_GPIO_IO_O
BEGIN axi_interconnect
 PARAMETER INSTANCE = axi_interconnect_1
 PARAMETER HW_VER = 1.06.a
 PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
 PORT INTERCONNECT_ACLK = processing_system7_0_FCLK_CLK0
 PORT INTERCONNECT_ARESETN = processing_system7_0_FCLK_RESET0_N
END

BEGIN axi_gpio
 PARAMETER INSTANCE = pushbuttons
 PARAMETER HW_VER = 1.01.b
 PARAMETER C_INTERRUPT_PRESENT = 1
 PARAMETER C_GPIO_WIDTH = 5
 PARAMETER C_BASEADDR = 0x41240000
 PARAMETER C_HIGHADDR = 0x4124ffff
 PARAMETER C_ALL_INPUTS = 1
 BUS_INTERFACE S_AXI = axi_interconnect_1
 PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
# PORT GPIO_IO = axi_gpio_1_GPIO_IO
 PORT GPIO_IO_I = net_pushbuttons_GPIO_IO_I_pin
END

BEGIN axi_timer
 PARAMETER INSTANCE = axi_timer_0
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_BASEADDR = 0x42800000
 PARAMETER C_HIGHADDR = 0x4280ffff
 BUS_INTERFACE S_AXI = axi_interconnect_1
 PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
END




----------------------------------------------------

Xilinx EDK disable IOB IOBs instantiated automatically

When tri-state ports are used in EDK (e.g. GPIO), and IOB will be automatically instantiated. This is because the FPGA has no internal bi-directional paths.

To avoid automatic insertation of the IOBs, GPIO should not be bi-directional.

Do not connect the GPIO_IO port, and instead, only connect the _I or _O ports


BEGIN axi_gpio
 PARAMETER INSTANCE = leds
 PARAMETER HW_VER = 1.01.b
 PARAMETER C_INTERRUPT_PRESENT = 1
 PARAMETER C_GPIO_WIDTH = 8
 PARAMETER C_BASEADDR = 0x41200000
 PARAMETER C_HIGHADDR = 0x4120ffff
 BUS_INTERFACE S_AXI = axi_interconnect_1
 PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0
 PORT GPIO_IO_O = leds_GPIO_IO_O
END


Monday, 10 September 2012

Xilinx SDK 14.2 xvtc.h:622:1: error: expected identifier or '(' before '}' token


Xilinx SDK 14.2, when trying to use Xilinx xvtc.h the Video Timing COntroller


"Compiling uartps"
"Compiling video timing controller"
In file included from xvtc.c:73:0:
xvtc.h:622:1: error: expected identifier or '(' before '}' token
In file included from xvtc_g.c:16:0:
xvtc.h:622:1: error: expected identifier or '(' before '}' token
In file included from xvtc_intr.c:70:0:
xvtc.h:622:1: error: expected identifier or '(' before '}' token
In file included from xvtc_sinit.c:72:0:
xvtc.h:622:1: error: expected identifier or '(' before '}' token
make[1]: *** [libs] Error 1


"Compiling cpu_cortexa9"
ERROR:EDK:369 -  make failed for target "libs"
ERROR:EDK:3418 - Error(s) while running make.
make: *** [ps7_cortexa9_0/lib/libxil.a] Error 2
make: Target `all' not remade because of errors.




Line 662 in xvtc.h is here:
#define XVtc_IntrSetLockPolarity(InstancePtr, LockPolarity) \
{ \
// THIS FUNCTION IS NOT NEEDED.
// THERE IS NO LOCK POLARITY.
// INCLUDED TO ALLOW OLDER SW TO COMPILE.
}

The comment lines to not have a trailing \, so the macro stops.

Solution should be to add the trailing '\'
This needs to be done in the "master" file, rather than the file in the project directory, which is auto-generated and deleted on a project clean.
C:\Xilinx\14.2\ISE_DS\EDK\sw\XilinxProcessorIPLib\drivers\vtc_v2_00_a\src


#define XVtc_IntrSetLockPolarity(InstancePtr, LockPolarity) \
{ \
// THIS FUNCTION IS NOT NEEDED. \
// THERE IS NO LOCK POLARITY.\
// INCLUDED TO ALLOW OLDER SW TO COMPILE.\
}